2018-11-06 HPC Meeting Minutes
Attendance
Committee Members
| Name | Present |
|---|---|
| Martin Stadtler (Sn Director of LDCG, Linaro) |  |
| Andrew Wafaa (Arm) | |
Pak Lui (Huawei) | |
Larry Wikelius (Cavium) |
|
Hongbo Zhang (HXT) | |
Jon Masters (RedHat) | |
Takeharu Kato (Fujitsu) |
|
| Koichi Hirai (Fujitsu) | |
| Kevin Pedretti (Sandia NL) | |
Guests
| Name | Present |
|---|---|
Kanta Vekaria (Office CTO, Linaro) |
|
| David Rusling, CTO Linaro | |
| Andrea Gallo (VP of Segment Groups, Linaro) |
|
| Anoop Saxena (Project Mgr Segments, Linaro) |
|
Renato Golin (HPC Tech Lead, Linaro) |
|
| Eric Van Hensbergen, Darren Cepulis, Brent Gorda (Arm) | |
| Andrew Young (Sandia) | |
| Ashwin (Cavium) | |
Agenda
- HPC Timeline
- OpenBlas
- HPC Asia
Next HPC SIG meeting on 27th Nov, agenda:
- Post SC18 Round up
- HPC Engineering update (Renato)
Minutes
OpenBLAS
- Concerns were raised that the micro-benchmarks may not be representative of actual use
- We should look into BLAS-Tester
- During the GitHub discussion, we're leaning towards making ARMv8 the new base standard and remove A57
- This would encompass all vanilla Arm cores: A53, A57, A72 and A73
- Using minimal settings from the manuals to guess caches and pipelines
- Dynamic Arch would throw a wrench at it again, as it would go back relying on runtime CPU detection
- Arm CPU detection has not followed what Intel has done (for better or worse) but hasn't come up with anything better (or even functional)
- We can use PPTT for caches (with some work), but that doesn't help cpuid for CPU vendor/part, which needs firmware support
- Eric has suggested we find a work around until support gets better
- Adding the files to /sys by hand (via bind mount or just plain copy)
- Add to OpenHPC's recipes, perhaps the Ansible playbooks?
- Everyone was in agreements that, regardless of good cpuid support, having a solid base is crucial